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ATmega128
Table 89. Status Codes for Master Receiver Mode
Status Code
Application Software Response
(T W SR)
Prescaler Bits
are 0
$08
Status of the Two-wire Serial
Bus and Two-wire Serial Inter-
face Hardware
A START condition has been
To/from T W DR
Load SLA+R
To T W CR
STA
0
STO
0
T W INT
1
T W EA
X
Next Action Taken by T W I Hardware
SLA+R will be transmitted
transmitted
ACK or NOT ACK will be received
$10
A repeated START condition
Load SLA+R or
0
0
1
X
SLA+R will be transmitted
has been transmitted
ACK or NOT ACK will be received
Load SLA+ W
0
0
1
X
SLA+ W will be transmitted
Logic will switch to master transmitter mode
$38
Arbitration lost in SLA+R or NOT
No T W DR action or
0
0
1
X
Two-wire Serial Bus will be released and not addressed
ACK bit
slave mode will be entered
No T W DR action
1
0
1
X
A START condition will be transmitted when the bus
becomes free
$40
SLA+R has been transmitted;
No T W DR action or
0
0
1
0
Data byte will be received and NOT ACK will be
ACK has been received
returned
No T W DR action
0
0
1
1
Data byte will be received and ACK will be returned
$48
SLA+R has been transmitted;
NOT ACK has been received
No T W DR action or
No T W DR action or
1
0
0
1
1
1
X
X
Repeated START will be transmitted
STOP condition will be transmitted and T W STO flag will
be reset
No T W DR action
1
1
1
X
STOP condition followed by a START condition will be
transmitted and T W STO flag will be reset
$50
Data byte has been received;
Read data byte or
0
0
1
0
Data byte will be received and NOT ACK will be
ACK has been returned
returned
Read data byte
0
0
1
1
Data byte will be received and ACK will be returned
$58
Data byte has been received;
NOT ACK has been returned
Read data byte or
Read data byte or
1
0
0
1
1
1
X
X
Repeated START will be transmitted
STOP condition will be transmitted and T W STO flag will
be reset
Read data byte
1
1
1
X
STOP condition followed by a START condition will be
transmitted and T W STO flag will be reset
Slave Receiver Mode
In the Slave Receiver mode, a number of data bytes are received from a master transmitter (see
Figure 100 ). All the status codes mentioned in this section assume that the prescaler bits are
zero or are masked to zero.
Figure 100. Data Transfer in Slave Receiver Mode
V CC
Device 1
SLAVE
Device 2
MASTER
Device 3
........
Device n
R1
R2
RECEIVER
TRANSMITTER
SDA
SCL
To initiate the Slave Receiver mode, T W AR and T W CR must be initialized as follows:
TWAR
TWA6
TWA5
TWA4
TWA3
TWA2
TWA1
TWA0
TWGCE
value
Device’s Own Slave Address
218
2467X–AVR–06/11
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